Nanolithography : the art of fabricating nanoelectronics, by Martin Feldman

By Martin Feldman

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18 um 4 Mb toggling MRAM’, IEEE IEDM Tech. , 995–9. 26. D. et al. (2003), ‘Magnetoresistive random access memory using magnetic tunnel junctions’, Proceedings of the IEEE, 91(5): 703–14. 27. C. (1996), ‘Current-driven excitation of magnetic multilayers’, Journal of Magnetism and Magnetic Materials, 159(1–2): p. L1–L7. 28. Demerjian, C. com, 16 November 2012. 29. -J. et al. (2010), ‘Fully integrated 54 nm STT-RAM with the smallest bit cell dimension for high density memory application’, IEEE IEDM Tech.

On Elect. and Struc. for MEMS, Australia. 39. , Scaravaggi, M. et al. (2004), ‘Novel μTrench phase-change memory cell for embedded and stand-alone non-volatile memory applications’, Symp. , pp. 18–19. 24 Advances in Non-volatile Memory and Storage Technology 40. , Zuliani, P. et al. (2004), ‘Phase-change memory technology for embedded applications’, Proc. ESSDERC 04, pp. 293–6. 41. , Jagasivamani, M. et al. (2008), ‘A multi-level-cell bipolar-selected phase-change memory’, Solid-State Circuits Conference, ISSCC, p.

3F2. It is clear that none of the alternative NVM so far discussed can be a serious contender as a NAND replacement in terms of cell costs. g. PCM41), its implementation and feasibility at the state-of-the-art lithography node is still to be demonstrated. In this scenario and considering the growing difficulties that must be faced for planar NAND scaling, there is strong interest in the so-called 3D NVM technologies. There are currently two main trends to develop 3D structures that can provide a higher integration density: cross point memory array, where several memory layers can be stacked, and the so-called 3D NAND, where the standard NAND strings are integrated along the vertical dimension (Fig.

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