By Frank Oppenheimer, Julio Luis Medina Pasaje
This e-book brings jointly a range of the easiest papers from the 17th variation of the discussion board on specification and layout Languages convention (FDL), which happened on October 14-16, 2014, in Munich, Germany. FDL is a well-established foreign discussion board dedicated to dissemination of study effects, sensible reviews and new rules within the software of specification, layout and verification languages to the layout, modeling and verification of built-in circuits, advanced hardware/software embedded structures, and mixed-technology systems.
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Extra resources for Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2014
Generic fault models, where each instance of a fault model can adapt the desired fault mode by generic configuration, and 4. e. fault injection, in a simulation automation platform . In the second section of this work, the motivation for this approach is clarified. The third section states the proposed fault injection technique. In the fourth section, a case study is presented where the previously described fault injection technique is applied to. The case study comprises a heterogeneous model of an automotive battery management system (BMS) module including twelve lithium-ion cells.
The tool Scoot  has been used to speed up simulations by synthesizing an optimized SystemC scheduler that performs partial-order reduction using information obtained from race analysis. In , the authors present a static data race detector that uses gcc plugin as a frontend. Similarly, a static race detector is given in  for ESL designs exploiting the dependency among atomic regions in SystemC simulations. This approach suffers from the lack of pointer analysis that leads to false positives.
F iff vce < vcf . Hence, they can be used to determine whether two actions are concurrent. A vector clock, vc, is a vector of integers where the size of the vector is determined by the number of processes. Initially, for a process j, vcj Œi D 0, for i ¤ j, and vcj Œj D 1. In this work, we assign a vector clock to every process. The vector clock is updated after synchronization operations. A process includes a copy of its vector clock in every outgoing message. On receiving a message, it updates its vector clock by taking a component-wise maximum with the vector clock included in the message.