By Arthur H.M. van Roermund, Herman Casier, Michiel Steyaert
Analog Circuit layout comprises in overall 18 tutorials. They mirror the contributions of 6 specialists in all the 3 fields coated via the 3 chapters pointed out within the subtitle, as offered on the fifteenth workshop on Advances in Analog Circuit layout (AACD) held in Maastricht, April 2006.
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Extra info for Analog Circuit Design: High-Speed A-D Converters, Automotive Electronics and Ultra-Low Power Wireless
But the trends and cost differences were compelling enough to stimulate us to investigate. Our first target for a CMOS ADC was for 8 bits at 4 GSa/s, aimed at replacing the above bipolar ADC with a lower-power and lower-cost CMOS ADC. We took the time-interleaved approach to an extreme: we would use many independent ADC “slices” operating in round-robin fashion to reach the desired sample rate. We settled on a number of new design principles: • Choose the core ADC architecture primarily for power efficiency of the unit converter rather than raw speed • Time-interleave as many slices as needed • Let currents and device sizes be optimized for SNR rather than matching • Use calibration to recover the necessary accuracy These principles were chosen to take advantage to the strength of CMOS: lots of transistors, low costs for digital logic.
So in a thermometer decoded array an element with an associated error is first activated and then the next activated element is placed on the opposite side of the array. 10 a . Binary. Fig. 10 b. Thermometer. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -3 Fig. 10 c. Symmetrical. Under the assumption of a linear error distribution this will then have the same error with the opposite sign. Fig. 10c shows the array used in Fig. 10a and Fig. 10b, but now the switch coding is implemented in a symmetrical way.
566-567, Feb 2006. 2V 6b 1GS/s Two-Step Subranging ADC”, IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 568-569, Feb 2006. 32 K. Poulton et al. 13µm CMOS”, IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 576-577, Feb 2006. 13um CMOS”, IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 574-575, Feb 2006.  P. Schvan, D. Pollex, S-C. Wang, C. Falt, N. Ben-Hamida, “A 22GS/s 5b ADC in 130nm SiGe BiCMOS”, IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb 2006.